Non-volatile memories are a desirable evolution in integrated circuit design due to their ability to maintain data absent a power supply. Phase-change materials, as well as other resistance variable materials, have been investigated for use in non-volatile memory cells. Phase-change memory cells include phase-change materials, such as chalcogenide alloys, which are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state and the resistance states distinguish the logic values of the memory cell. For example, a memory element in an amorphous state exhibits a relatively high resistance and a memory element in a crystalline state exhibits a relatively low resistance, each of which can be sensed as stored data.
A typical phase-change memory cell has a layer of phase-change material between first and second electrodes. As an example, the phase-change material can be a chalcogenide alloy, such as Ge2Sb2Te5 or AgInSbTe. When used in a memory device, a portion of the phase-change material is set to a particular resistance state according to the amount of current applied via the electrodes. To obtain an amorphous state, a relatively high write current pulse (a reset pulse) is applied through the phase-change cell to melt a portion of the material for a first period of time. The current is removed and the cell cools rapidly to a temperature below its crystallization temperature, which results in a portion of the material having an amorphous phase. To obtain a crystalline state, a lower current write pulse (a set pulse) is applied to the phase-change cell for a second period of time (typically longer in duration than the first period of time) to heat the material to a temperature below its melting point, but above its crystallization temperature. This causes the amorphous portion of the material to re-crystallize to a crystalline phase that is maintained once the current is removed and the cell is cooled.
The typically large programming current of phase-change memory devices is a limiting factor in reducing the memory cell size. The programmable volume of phase-change memory cell and programming current requirement are dependent on the area of the bottom electrode in contact with the memory element of the cell. To reduce such current, it is desirable to reduce the effective bottom electrode area in contact with the cell.
One issue effecting resistance-based memory, such as phase change memory, functionality is the non-uniformity of bottom electrode area. Non-uniformity in bottom electrode size across a memory array leads to non-uniformity of programming current requirement for different memory cells of the array, which makes it difficult to design a circuit that can accommodate the variation between bits. Undesired variation in bottom electrode size causes set and reset resistance distribution overlap, which, in the worst case, makes establishing a sensing scheme for all bits of an array impossible. Reduction in bottom electrode size should be combined with electrode size uniformity to achieve an ideal contact for a resistance memory device.
One technique used to reduce bottom electrode size has been to employ anisotropically etched spacers in a via to make contacts smaller than the photolithographic limit. This technique gives rise to large variations in contact size since variations in chemical mechanical polishing (CMP) and via edge rounding cause the contacts to have different heights and cross-sections and thus different contact areas with respect to an overlying memory element.
Another technique used to reduce bottom electrode size has been to use ring shaped contacts. FIGS. 1a-1d show two such ring shaped contacts 20 formed over the same substrate simultaneously, but having different dimensions due to processing variances. FIG. 1c shows the contact 20 shown in cross section a-a′ of FIG. 1a from above. FIG. 1d shows the contact 20 shown in cross section b-b′ of FIG. 1b from above. Such contacts 20 have been formed simultaneously by etching a via 14 into a dielectric layer 12 to expose a conductive layer 10 (which can be over a substrate 1). A conductive liner 16 is deposited conformally within the via 14, along its bottom, over the conductive layer 10, and along the via's sidewalls. Another dielectric material 18, such as silicon oxide, is deposited over the conductive liner 16 and within the via 14. A CMP step removes both the conductive liner 14 and dielectric material 18, stopping in the dielectric layer 12, so that an exposed ring of conductive liner 16 remains as a contact 20 as shown in FIGS. 1c and 1d. 
As shown in the side-by-side comparisons of the contact 20 of FIGS. 1a and 1c and the contact 20 of FIGS. 1b and 1d, ring shaped contacts 20 formed simultaneously over the same substrate 10 can have different cross sectional areas even when the conductive liner 16 is the same thickness in both vias 14 due to process variations in CMP height in combination with via 14 sidewall slope variation and rounding of via 14 edges.
There have been attempts to resolve the problems of the prior art relating to the rounded edge of via and CMP height variations. For example, a two-step CMP process, as shown in FIGS. 2a-2d, has been proposed where a layer of silicon oxide 12b is formed over a layer of silicon oxynitride 12a and the contact via 14a is formed through both to an underlying conductive layer 10a. FIG. 2c shows the contact 20a shown in cross section c-c′ of FIG. 2a from above. FIG. 2d shows the contact 20a shown in cross section d-d′ of FIG. 2b from above. After forming the conformal conductive liner 16b in the via 14a, with a conformal silicon nitride layer 16a thereunder, and a silicon oxide plug 18a over each, a first CMP step is used to remove the conformal conductive liner 16b, the silicon oxide plug 18a, and part of the silicon oxide layer 12a, stopping part-way through the silicon oxide layer 12b. An etch-back step removes the silicon oxide layer 12b and exposes the silicon oxynitride layer 12a. A second CMP step flattens the contacts 20a to a uniform height.
The above proposed process does potentially resolve CMP height variation and via edge rounding issues. However, due to via 14a slope variation, the contacts 20a formed simultaneously by such a technique will still tend to vary in size and shape, as shown by the comparison between the contact 20a shown in FIGS. 2a and 2c and the contact shown in FIGS. 2b and 2d, which leads to the same programming problems as the other techniques discussed above.
It is desirable to mitigate processing variability and provide more consistently shaped contacts for electrodes.